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fn7931 rev 3.00 page 1 of 13 september 20, 2012 fn7931 rev 3.00 september 20, 2012 isl9307 3mhz dual 1500ma step-down conver ters and dual low-input ldos datasheet the isl9307 is an integrated mini power management ic (mini-pmic) ideal for applications for powering low-voltage microprocessor or multiple voltage rails with a battery as an input source, such as a single li-ion or li-polymer. isl9307 integrates two high-efficiency, 3mhz, synchronous step-down converters (dcd1 and dcd2) and two low-input, low-dropout linear regulators (ldo1 and ldo2). the 3mhz pwm switching frequency allows the use of very small external inductors and capacitors. both step-down converters can enter skip mode under light load conditions to further improve efficiency and maximize battery life. the isl9307 features en pins for each channel, thus allowing startup delay for power sequencing. the isl9307 also provides two 300ma low-dropout (ldo) regulators. the input voltage range is 1.5v to 5.5v, which allows them to be powered from one of the on-chip step-down converters or directly from a battery. the default ldo power-up output comes with factory pre-set fixed output voltage options between 0.9v and 3.3v. the isl9307 is available in a 4mmx4mm 16 ld tqfn. features ? dual 1500ma, synchronous step-down converters and dual 300ma, general-purpose ldos ? input voltage range - dcd1/dcd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5v to 5.5v - vinldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5v to 5.5v ? adjustable output voltage - vodcd1/vodcd2 . . . . . . . . . . . . . . . . . . . . . . . . 0.8v to v in ?50 a i q (typ) with dcd1/dcd2 in skip mode; 20 a i q (typ) for each enabled ldo ? en pins for dcd1/dcd2 and ldo1/ldo2 ? small, thin, 4mmx4mm tqfn applications ? cellular phones, smart phones ? pdas, portable media players, portable instruments ? single li-ion/li-polymer battery-powered equipment ?dsp core power figure 1. typical application diagram is l9307 l 1 = 1.5h 2.5v to 5.5v 1500ma 1500ma 1.5v to 5.5v 300ma 300ma r 1 r 2 r 3 r 4 1f c 2 l 2 = 1.5h c 4 10f c 5 10f c 6 1f c 7 1f endcd1 vindcd1 vinldo vindcd2 endcd2 enldo1 enldo2 gnddcd1 gnddcd2 gndldo c 1 10f voldo2 sw1 fb1 sw2 fb2 voldo1 note: only for adjustable output version. for fixed output version, directly connect the fb pin to the output of the buck converter.
isl9307 fn7931 rev 3.00 page 2 of 13 september 20, 2012 block diagram table 1. typical application part list parts description manufacturer part number specifications size l1, l2 inductor sumida cdrh2d14np-1r5 1.5h/1.80a/50m 3.0mmx3.0mmx1.55mm c1 input capacitor murata grm21br60j106ke19l 10f/6.3v 0805 c2, c3 input capacitor murata grm185r60j105ke26d 1f/6.3v 0603 c4, c5 output capacitor murata grm21br60j106ke19l 4.7f/6.3v 0805 c6, c7 output capacitor murata grm185r60j105ke26d 10f/6.3v 0603 r1, r2, r3, r4 resistor various 1%, smd, 0.1 0603 ldo1 300ma dcd2 buck converter vindcd1 fb1 sw1 gnddcd1 vindcd2 fb2 sw2 gnddcd2 voldo1 voldo2 enldo1 enldo2 endcd1 gndldo 10f 1f 1f 10f 4.7f 4.7f 1f 1.5h 1.5h dcd1 buck converter over- current protection analog/logic circuit input thermal shutdown ldo2 300ma short circuit protection endcd2 vinldo
isl9307 fn7931 rev 3.00 page 3 of 13 september 20, 2012 pin configuration isl9307 (16 ld 4x4 tqfn) top view 12 11 10 9 16 15 14 13 5 6 7 8 1 2 3 4 vindcd1 fb1 endcd1 enldo1 vindcd2 fb2 endcd2 gndldo sw1 gndcdc1 gnddcd2 sw2 vinldo voldo1 voldo2 enldo2 e-pad pin descriptions pin number (tqfn) name description 1 vindcd1 input voltage for buck converter dcd1 and power supply pin for all internal digital/ analog circuits. 2 fb1 feedback pin for dcd1; connect external voltage divider resistors between dcdc1 output, this pin, and ground. for fixed output versions, connect this pin directly to the dcd1 output. 3 endcd1 enable pin for dcd1. tie high or low. do not float. 4 enldo1 enable pin for ldo1. tie high or low. do not float. 5 vinldo input voltage for ldo1 and ldo2 6 voldo1 output voltage of ldo1 7 voldo2 output voltage of ldo2 8 enldo2 enable pin for ldo2. tie high or low. do not float. 9 gndldo power ground for ldo1 and ldo2 10 endcd2 enable pin for dcd2. tie high or low. do not float. 11 fb2 feedback pin for dcd2; connect external voltage divider resistors between dcd2 output, this pin, and ground. for fixed output versions, connect this pin directly to the dcd2 output. 12 vindcd2 input voltage for buck converter dcd2 13 sw2 switching node for dcd2; connect to one terminal of the inductor. 14 gnddcd2 power ground for dcd2 15 gnddcd1 power ground for dcd1 16 sw1 switching node for dcd1; connect to one terminal of the inductor. e-pad e-pad exposed pad; connect to system ground.
isl9307 fn7931 rev 3.00 page 4 of 13 september 20, 2012 ordering information part number (notes 1, 2, 3) part marking fbsel dcd1 (v) fbsel dcd2 (v) slv ldo1 (v) slv ldo2 (v) temp. range (c) package (pb-free) pkg. dwg. # isl9307irtaajbz-t 9307i aajbz adj adj 2.8 1.5 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaajbz-t7a 9307i aajbz adj adj 2.8 1.5 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaajfz-t 9307i aajfz adj adj 2.8 2.5 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaajfz-t7a 9307i aajfz adj adj 2.8 2.5 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaajgz-t 9307i aajgz adj adj 2.8 2.7 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaajgz-t7a 9307i aajgz adj adj 2.8 2.7 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaajlz-t 9307i aajlz adj adj 2.8 2.9 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaajlz-t7a 9307i aajlz adj adj 2.8 2.9 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaajyz-t 9307i aajyz adj adj 2.8 0.9 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaajyz-t7a 9307i aajyz adj adj 2.8 0.9 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaancz-t 9307i aancz adj adj 3.3 1.8 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaancz-t7a 9307i aancz adj adj 3.3 1.8 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaanfz-t 9307i aanfz adj adj 3.3 2.5 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaanfz-t7a 9307i aanfz adj adj 3.3 2.5 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaangz-t 9307i aangz adj adj 3.3 2.7 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaangz-t7a 9307i aangz adj adj 3.3 2.7 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaanlz-t 9307i aanlz adj adj 3.3 2.9 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaanlz-t7a 9307i aanlz adj adj 3.3 2.9 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaanwz-t 9307i aanwz adj adj 3.3 1.2 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaanwz-t7a 9307i aanwz adj adj 3.3 1.2 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaanyz-t 9307i aanyz adj adj 3.3 0.9 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaanyz-t7a 9307i aanyz adj adj 3.3 0.9 -40 to +85 16 ld tqfn l16.4x4g isl9307irtwcnjz-t 9307i wcnjz 1.2 1.8 3.3 2.8 -40 to +85 16 ld tqfn l16.4x4g isl9307irtwcnjz-t7a 9307i wcnjz 1.2 1.8 3.3 2.8 -40 to +85 16 ld tqfn l16.4x4g isl9307irtwcwnz-t 9307i wcwnz 1.2 1.8 1.2 3.3 -40 to +85 16 ld tqfn l16.4x4g isl9307irtwcwnz-t7a 9307i wcwnz 1.2 1.8 1.2 3.3 -40 to +85 16 ld tqfn l16.4x4g isl9307irtaajbev1z evaluation board isl9307irtaajfev1z evaluation board isl9307irtaajgev1z evaluation board isl9307irtaajlev1z evaluation board isl9307irtaajyev1z evaluation board isl9307irtaancev1z evaluation board ISL9307IRTAANFEV1Z evaluation board isl9307irtaangev1z evaluation board isl9307irtaanlev1z evaluation board isl9307irtaanwev1z evaluation board isl9307irtaanyev1z evaluation board isl9307irtwcnjev1z evaluation board isl9307irtwcwnev1z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl9307 . for more information on msl please see tech brief tb363 .
isl9307 fn7931 rev 3.00 page 5 of 13 september 20, 2012 absolute maximum ratings (refer to ground) thermal information sw1, sw2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5v to 6.5v fb1, fb2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 3.6v gnddcd1, gnddcd2, gndldo. . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v esd ratings human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . .3.5kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 225v charged device model (tested per jesd22-c101d) . . . . . . . . . . . .2.2kv latch up (tested per jesd78b, class ii, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) 16 ld tqfn package (note 4). . . . . . . . . . . . . . . . . . . . . 40.2 maximum junction temperature range . . . . . . . . . . . . . .-40c to +150c recommended junction temperature range . . . . . . . . .-40c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c recommended operating conditions vindcd1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5v to 5.5v vindcd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3v to vindcd1 vinldo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5v to vindcd1 dcd1 and dcd2 output current . . . . . . . . . . . . . . . . . . . . 0ma to 1500ma ldo1 and ldo2 output current . . . . . . . . . . . . . . . . . . . . . . 0ma to 300ma operating ambient temperature . . . . . . . . . . . . . . . . . . . . . -40 c to +85 c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . electrical specifications unless otherwise noted, typical specifications are measured at the fo llowing conditions: t a = +25c, vindcd1 = 3.6v, vindcd2 = 3.3v. fo r ldo1 and ldo2, vinldo = voldo + 0.5v to 5.5v with vinldo always no higher than vindcd1. l 1 ? = ? l 2 = 1.5h, c 1 = c 4 = c 5 = 10f, c 2 = c 6 = c 7 = 1f, i out = 0a for dcd1, dcd2, ldo1 and ldo2 (see ? figure 1 on page 1 for more details). boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 5) typ max (note 5) unit vindcd1, vindcd 2 voltage range 2.5 - 5.5 v vindcd1, vindcd2 undervoltage lockout threshold v uvlo rising - 2.2 2.3 v falling 1.9 2.1 - v quiescent supply current on vindcd1 i vin1 only dcd1 enabled; no load and no switching on dcd1 -40 60 a i vin2 only dcd1 and ldo1 enabled; no load and no switching on dcd1 -60 95 a i vin3 both dcd1 and dcd2 enabled; no load and no switching on both dcd1 and dcd2 -50 75 a i vin4 only ldo1 and ldo2 enabled - 110 130 a i vin5 dcd1, dcd2, ldo1 and ldo2 enabled; no load and no switching on both dcd1 and dcd2 -135 160 a shutdown supply current i sd vindcd1 = 5.5v; dcd1, dcd2, ldo1 and ldo2 disabled -0.15 5 a thermal shutdown - 155 - c thermal shutdown hysteresis -30-c dcd1 and dcd2 fb1, fb2 regulation voltage v fb 0.785 0.8 0.815 v fb1, fb2 bias current i fb fb = 0.75v - 0.001 - a output voltage accuracy v in = v o + 0.5v to 5.5v (minimal 2.5v), 1ma load -3 - +3 % line regulation v in = v o + 0.5v to 5.5v (minimal 2.5v) - 0.1 - %/v maximum output current 1500 --ma
isl9307 fn7931 rev 3.00 page 6 of 13 september 20, 2012 p-channel mosfet on-resistance v in = 3.6v, i o = 200ma - 0.14 0.20 v in = 2.3v, i o = 200ma - 0.24 0.40 n-channel mosfet on-resistance v in = 3.6v, i o = 200ma - 0.11 0.20 v in = 2.3v, i o = 200ma 0.18 0.34 p-channel mosfet peak current limit i pk 2.1 2.5 2.75 a sw maximum duty cycle -100- % sw leakage current v in = 5.5v - 0.005 1 a pwm switching frequency f s 2.6 3.0 3.4 mhz sw minimum on-time v fb = 0.75v - 70 - ns bleeding resistor - 115 - ldo1 and ldo2 vinldo supply voltage no higher than vindcd1 1.5 - 5.5 v vinldo undervoltage lock-out threshold v uvlo vindcd1 = 2.3v, rising - 1.41 1.46 v vindcd1 = 2.3v, falling 1.33 1.37 - v internal peak current limit 350 425 540 ma dropout voltage i o = 300ma, vo 2.1v - 125 250 mv i o = 300ma, 2.1v < vo 2.8v - 100 200 mv i o = 300ma, vo > 2.8v - 80 170 mv power supply rejection ratio i o = 300ma @ 1khz, v in = 3.6v, vo = 2.6v, t a = +25c -55-db output voltage noise v in = 4.2v, i o = 10ma, t a = +25c, bw = 10hz to 100khz -45-v rms enable pin logic endcd1, endcd2, enldo1, enldo2 pin logic high 1.4 v endcd1, endcd2, enldo1, enldo2 pin logic low 0.4 v enable pin leakage current 0.05 1 a note: 5. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications unless otherwise noted, typical specifications are measured at the fo llowing conditions: t a = +25c, vindcd1 = 3.6v, vindcd2 = 3.3v. fo r ldo1 and ldo2, vinldo = voldo + 0.5v to 5.5v with vinldo always no higher than vindcd1. l 1 ? = ? l 2 = 1.5h, c 1 = c 4 = c 5 = 10f, c 2 = c 6 = c 7 = 1f, i out = 0a for dcd1, dcd2, ldo1 and ldo2 (see ? figure 1 on page 1 for more details). boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 5) typ max (note 5) unit
isl9307 fn7931 rev 3.00 page 7 of 13 september 20, 2012 theory of operation dcd1 and dcd2 both the dcd1 and dcd2 converters on isl9307 use the peak-current-mode pulse-width modulation (pwm) control scheme for fast transient respon se and pulse-by-pulse current limiting. both converters are ab le to supply up to 1500ma load current. under light load conditions, the device enters a pulse-skipping mode to minimize switching loss by reducing switching frequency. figure 2 illustrates the skip mode operation. a zero-cross sensing circuit monito rs the current flowing through the sw node for zero crossing. when it is detected to cross zero for 16 consecutive cycles, the regulator enters skip mode. during the 16 consecutive cycles, the inductor current could be negative. the counter is reset to zero when the sensed current flowing through the sw node does not cro ss zero during any cycle within the 16 consecutive cycles. once the converter enters skip mode, the pulse modulation is controlled by an internal comparator while each pulse cycle remains synchronized to the pwm clock. the p-channel mosfet is turned on at the rising edge of the clock and turned off when its current reaches ~20% of the peak current limit. as the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle-over- cycle. when the output voltage is sensed to reach 1.5% above its nominal voltage, the p-channel mosfet is turned off immediately, and the inductor current is fully discharged to zero and stays at zero. the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-channel mosfet turns on again, repeating the previous operations. the regulator resumes normal pwm mode operation when the output voltage is sensed to dr op below 1.5% of its nominal voltage value, as shown in figure 3. 16 cycles clock i l v out 0 v out_nominal 20% peak current limit 1.015*v out_nominal figure 2. skip mode operation waveforms v eamp d i l v out v csa figure 3. pwm operation waveforms
isl9307 fn7931 rev 3.00 page 8 of 13 september 20, 2012 soft-start soft-start reduces the in-rush curren t during the start-up stage. the soft-start block limits the current rising speed so that the output voltage rises in a controlled fashion. overcurrent protection the isl9307 provides overcurrent pr otection for dcd1 and dcd2 for when an overload condition occurs. when the current at p-channel mosfet is sensed to reach the current limit, the internal protection circuit is triggered to turn off the p-channel mosfet immediately. dcd short-circ uit protection the isl9307 provides short-circuit protection for both dcd1 and dcd2. the feedback voltage is monitored for output short-circuit protection. when the output voltage is sensed to be lower than a certain threshold, the internal circuit will change the pwm oscillator frequency to a lower frequenciy to protect the ic from damage. the p-channel mosfet peak current limit remains active during this state. undervoltage lockout (uvlo) an undervoltage lockout (uvlo) ci rcuit is provided on isl9307. the uvlo circuit block can prev ent abnormal operation in the event that the supply voltage is too low to guarantee proper operation. the uvlo on vindcd1 is set for a typical 2.2v with 100mv hysteresis. vinldo is set for a typical 1.4v with 50mv hysteresis. when the input voltage is sensed to be lower than the uvlo threshold, the related channel is disabled. low dropout operation both dcd1 and dcd2 converters feature low dropout operation to maximize battery life. when the input voltage drops to a level at which the converter can no longer operate under switching regulation to maintain the output voltage, the p-channel mosfet is completely turned on (100% duty cycle). the dropout voltage under such a condition is the prod uct of the load current and the on-resistance of the p-channel mosfet. minimum required input voltage (v in ) under such a condition is the sum of output voltage plus voltage drop across the inductor and the p-channel mosfet switch. active output voltage discharge for dcd1, dcd2 the isl9307 offers a feature to actively discharge the output voltage of dcd1 and dcd2 via an internal bleeding resistor (typical 115 ) when the channel is disabled. thermal shutdown the isl9307 provides a built-in thermal protection function with thermal shutdown threshold temperature set at +155c with +25c hysteresis (typical). when the die temperature is sensed to reach +155c, the regulator is completely shut down, and as the temperature is sensed to drop to +130c (typical), the device resumes normal operation, starting from soft-start. board layout recommendations the isl9307 is a high frequency switching charger and hence the pcb layout is a very important design practice to ensure a satisfactory performance. the power loop is composed of the output inductor, l; the output capacitor, c out ; the sw pin; and the pgnd pin. it is important to make the power loop as small as possible, and the connecting traces among them should be di rect, short and wide. the same practice should be applied to the connection of the vin pin; the input capacitor, c in ; and pgnd. the switching node of the converter, the sw pin, and the traces connected to this node are very noisy, so keep the voltage feedback trace and other noise-sensitive traces away from these noisy traces. the input capacitor should be placed as close as possible to the vin pin. the ground of the input and output capacitors should be connected as close as possible as well. in addition, a solid ground plane is helpful for good emi performance. the isl9307 employs a thermally enhanced tqfn package with an exposed pad. the exposed pad should be properly soldered onto the thermal pad of the board to remove heat from the ic. the thermal pad should be big enough for nine vias, as shown in figure 4. figure 4. exposed thermal pad
isl9307 fn7931 rev 3.00 page 9 of 13 september 20, 2012 typical operating conditions figure 5. dcd output ripple (v in = 4.2v, pfm, time scale = 1s) ch1: vodcd1 (20mv/div), ch2: il1 (500ma/div), ch3: vodcd2 (20mv/div), ch4: il2 (500ma/div) figure 6. dcd output ripple (v in = 4.2v, full loading @ vodcd1 and vodcd2, time scale = 200ns) ch1: sw1 (5v/div), ch2: vodcd1 (20ma/div), ch3: sw2 (5v/div), ch4: vodcd2 (20ma/div) figure 7. inductor current ripple (v in = 3.6v, pfm, time scale = 200ns) ch1: sw1 (2v/div), ch2: il1 (200ma/div), ch3: sw2 (2v/div), ch4: il2 (200ma/div) figure 8. inductor current ripple (v in = 3.6v, full loading, pwm, time scale = 200ns) ch1: sw1 (2v/div), ch2: il1 (500ma/div), ch3: sw2 (2v/div), ch4: il2 (500ma/div)
isl9307 fn7931 rev 3.00 page 10 of 13 september 20, 2012 figure 9. dcd1 transient response (v in = 3.6v, step load: 150ma to 1500ma) ch1: vodcd1 (100mv/div, ac), ch2: vodcd2 (50mv/div, ac, ch4: il4 (500ma/div) figure 10. dcd2 transient response (v in = 3.6v, step load: 150ma to 1500ma) ch1: vodcd1 (100mv/div, ac), ch2: vodcd2 (50mv/div, ac, ch4: il4 (500ma/div) figure 11. enable waveform ch1: endcd1/endcd2/enldo1/enldo2 (5v/div), ch2: vodcd1: (2v/div), ch3: vodcd2 (2v/div), ch4: voldo1 (1v/div) figure 12. 4-channel power-up after enable ch1: voldo1 (1v/div), ch2: vodcd1 (2v/div), ch3: vodcd2 (2v/div), ch4: voldo2 (1v/div) figure 13. efficiency vs load (v out = 1.8v, pfm/pwm) figure 14. efficiency vs load (v out = 1.2v, forced pwm) typical operating conditions (continued) 30 40 50 60 70 80 90 100 1 10 100 1000 10000 output current (ma) efficiency (%) v in = 3.6v v in = 5.5v v in = 2.8v 30 40 50 60 70 80 90 1 10 100 1000 10000 v in = 3.6v v in = 5.5v v in = 2.8v output current (ma) efficiency (%)
isl9307 fn7931 rev 3.00 page 11 of 13 september 20, 2012 i figure 15. dcd output voltage vs output current (v out = 1.8v, pfm/pwm) figure 16. dcd output voltage vs output current (v out = 1.2v, pfm/pwm) figure 17. ripple rejection ratio vs frequency f igure 18. quiescent current vs input voltage typical operating conditions (continued) 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1 10 100 1000 10000 v in = 3.6v v in = 5.5v v in = 2.8v output current (ma) output voltage (v) 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1 10 100 1000 10000 v in = 3.6v v in = 5.5v v in = 2.8v output current (ma) output voltage (v) 0 10 20 30 40 50 60 70 0.1 1 10 100 1000 frequency (khz) power supply rejection ratio (db) v in = 3.6v v out = 2.6v load = 300ma psrr 40 42 44 46 48 50 52 54 56 58 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input voltage (v) v o = 1.2v dcd1 = dcd2 = no switching, no load ldo1 = ldo2 = disabled quiescent current (a) -40c +25c +85c
fn7931 rev 3.00 page 12 of 13 september 20, 2012 isl9307 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2012. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: isl9307 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change july 24, 2012 fn7931.3 page 5 - abs max ratings, esd ratings changed from: machine model (tested per jesd22-a115-a). . . . . .2.2kv charged device model (tested per jesd22-c101d). . .225v to: machine model (tested per jesd22-a115-a). . . . . .225v charged device model (tested per jesd22-c101d). . .2.2kv february 24, 2012 fn7931.2 initial release to web.
isl9307 fn7931 rev 3.00 page 13 of 13 september 20, 2012 package outline drawing l16.4x4g 16 lead thin quad flat no-lead plastic package rev 0, 4/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view jedec reference drawing: mo220k. 7. 2 . 10 0 . 10 see detail "x" 0.30 0.05 base plane pin #1 5 8 ( 3 . 6 typ ) ( 2 . 10 ) ( 12x 0 . 65 ) ( 16x 0 . 30 ) ( 16 x 0 . 70 ) 0.75 0 . 2 ref 0 . 00 min. 0 . 05 max. c 5 4 0.10 c m index area (4x) 0.15 pin 1 6 4.00 12 4.00 9 a b 4 0.65 12x 13 4x 1.95 16 1 6 0.08 c c seating plane 0.10 c a b 16x 0 . 50 0 . 1 index area

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